There are various known methods for representing serial digital data. For example, serial digital data can be represented as a polarity-free scrambled NRZI (Non-Return-to-Zero-Inversion) sequence generated with two fixed polynomials implemented as linear feedback shift registers. There are also SMPTE standards describing bit-parallel digital interfaces for various analog signals and serial digital interfaces for these bit-parallel digital signals. Subsequently, there are a multitude of systems which use various serial digital video signals having differing data rates. For example, in analog video signals, the timing information will depend on the horizontal line frequency, which is typically controlled by a timing signal known as the horizontal sync. In the NTSC video standard, the composite video signal has 525 horizontal lines every frame with 29.97 frames per second, so that the resultant horizontal line frequency is 15.734 kHz. In the PAL video standard, the composite video signal has 625 horizontal lines every frame with 25 frames per second, resulting in a horizontal line frequency of 15.625 kHz. For composite video, one timing reference signal (TRS) per horizontal line is present in the digital signal to identify the horizontal sync timing signal. On the other hand, a component video signal (in the form of one luminance and two colour-difference components) will have two timing reference signals per horizontal line in digital signal, although the component video will have the same line frequency as its composite counterpart. The two TRS's identify the end-of-active-video (EAV) and the start-of-active-video (SAV) timing references.
According to the known SMPTE (Society of Motion Picture and Television Engineers) 259M standard, the bit rates of the serial digital signals for the above horizontal rates are defined with either 4:2:2 component or 4 f.sub.sc composite digital signals. The component signals have the same bit rates for either the 525 or 625 line systems, and have a 270 megabit/second bit rate for 13.5 MHz luminance sampling and 360 megabit/second for 18 MHz luminance sampling. For the composite video signals, the bit rate for composite NTSC 4 f.sub.sc signals is 143 megabits/second and for composite PAL 4 f.sub.sc signals is 177.3 megabits/second.
A phase lock loop (PLL) is a known circuit which is used in data communication receivers to lock the phase of a voltage-controlled oscillator (VCO) to the incoming data stream and thereby recover the clock signal from the data. The clock signal is subsequently used to sample the incoming data in order to generate a new data signal which has been re-timed or synchronized with the recovered clock signal. Since the clock signal is derived from the voltage controlled oscillator, both the recovered clock and the re-timed data are relatively free from "timing jitter". The data and clock signals are then fed into a descrambler. Descramblers are used to transform and decode the scrambled serial digital stream into the original unscrambled serial data stream. The unscrambled data stream is then shifted into a deserializer which converts serial data into parallel data (e.g. ten-bit). The deserializer detects the timing reference signal (TRS) in order to set the ten-bit word boundary for the parallel outputs.
It will be appreciated that where a system is designed to be capable of extracting the clock signal from various digital video data streams having a range of bit rates, the voltage controlled oscillator must have a wide tuning range. Unfortunately, a wide tuning range can lead to the VCO locking to a harmonic and thereby result in an incorrect clock signal. In addition, in systems where the exact bit rate is not known but is within a set of given bit rates, it is desirable to know at which bit rate the phase locked loop has locked. To avoid locking on a harmonic and to determine the bit rate at which the phase lock loop has locked, known voltage controlled oscillators are typically designed to have a narrow tuning range with selectable center frequencies that are appropriate for given serial digital bit rates. To avoid the possibility of locking to a harmonic when the center frequency is automatically selected, the system will include a descrambler and deserializer to detect the timing reference signal in order to indicate whether the extracted clock signal and re-timed data are valid or invalid. In these known systems, if a timing reference signal is detected, it follows that the desired center frequency setting for the voltage controlled oscillator has been selected. If the timing reference signal has not been detected after an appropriate amount of time, a different center frequency setting is selected and this process is repeated until the timing reference signal is detected.
One of the problems with these prior art systems is that it is difficult for a voltage controlled oscillator to maintain low phase noise over a wide range of oscillation frequencies. One known approach to this problem involves reducing the range a voltage controlled oscillator is required to be tuned by inserting a dual modulus frequency divider in the feedback loop of the phase lock loop. The modulus for the dual frequency divider is selected to be one or two. Thus, for a given input to the phase lock loop, the voltage controlled oscillator frequency will be two times higher when a divider modulus is two than when it is one. In such a system, the clock is now derived from the output of the divider, and hence not affected by the divider modulus selection.
The process of bringing a phase locked loop into lock is termed acquisition, or if the loop acquires lock by itself then it is termed pull-in. It is known that this ability to lock is limited by the loop band width and often only achievable in practical systems with some assistance. One known method which is used to assist in locking a phase locked loop is known as frequency sweeping method. Frequency sweeping uses auxiliary circuits to reliably achieve lock. A typical frequency sweep circuit comprises a constant current which is fed into the integrator of the loop filter. The output is a ramp which is used to control the voltage controlled oscillator, thereby sweeping the voltage controlled oscillator frequency. Once the phase locked loop has acquired lock, the current is shut off and the integrator has been charged to the correct voltage needed by the voltage controlled oscillator.
Another problem with phase locked loop circuits for digital serial applications arises from the temperature dependence, i.e. drift, of the voltage controlled oscillator. In practical systems, the voltage controlled oscillator can have a relatively large temperature dependence. For a phase locked loop with a wide tuning range, temperature drift is normally not a problem because it can be compensated by the feedback loop. However, in phase locked loops having a narrow tuning range, i.e. for serial digital applications, the temperature dependence of the voltage controlled oscillator can be outside the loop adjustment range. Therefore, the ability of the phase locked loop to correct for temperature drifts in the voltage controlled oscillator can be greatly limited and temperature dependence becomes a problem because it can affect performance of the phase locked loop and digital receiver.
Accordingly, there is a need for a control circuit for use with a phase locked loop in a digital receiver which can provide automatic fine tuning and aided acquisition for the phase locked loop stage. The automatic fine tuning circuit should have a low time constant so that there is little or no effect on the characteristics of the phase locked loop. Furthermore, in a digital video application, there is a need to have a clock recovery system which can differentiate between composite video and component video.